Various methods and circuits are used for microprocessor-based systems to provide a clock signal whose frequency may be varied to accommodate system constraints. For example, if the microprocessor must communicate with relatively slow speed peripheral devices, it is desirable to reduce the frequency of the clock signal provided to the microprocessor to accommodate the access time required by the peripheral devices. A variable frequency microprocessor clock generator for this type of application is described in U.S. Pat. No. 4,819,164 issued to Branson.
A similar feature is incorporated in the Compaq DESKPRO 386/20 system in which an "auto" mode allows the processor to operate at full speed except during diskette operations when the speed is reduced. This system can also be operated at one of a number of predetermined frequencies to simulate other processor systems.
A particular incentive for providing a variable frequency clock signal to a microprocessor fabricated with CMOS or CHMOS architecture is that the power dissipation of such a device is proportional to the clock frequency. Therefore, in order to reduce the active system power, it is desirable to reduce the clock frequency to the processor to the maximum extent consistent with maintaining system performance objectives. Furthermore, it is desirable to stop the processor clock altogether if the processor would otherwise be in an idle state. The Harris 82C85 CMOS Static Clock Controller/Generator provides a clock signal that may be at the full frequency of an external oscillator, at a divide-by-256 frequency, or that may be stopped.
Prior art variable frequency clock generators will generally produce a "glitch" when dynamically switching between clock frequencies. At the frequency transition, a clock cycle of indeterminate duration is likely to be produced. If this clock period is less than a minimum value tolerated by the microprocessor, a system anomaly may occur.
One of the objectives of the present invention is to provide a variable frequency clock generator that may be dynamically switched between frequencies such that the duration of every clock cycle is at least as great as the clock cycle duration of the highest operating frequency.